1. Filed of the Invention
The present invention relates to a bipolar complementary metal oxide semiconductor (BiCMOS) push-pull type logic apparatus incorporating a voltage clamp circuit.
2. Description of the Related Art
A prior art BiCMOS push-pull type logic apparatus such as an inverter includes a push-pull buffer formed by two NPN type transistors, and a CMOS control circuit for controlling the bases of the NPN type transistors in response to an input voltage. That is, one of the NPN type transistors is turned ON, while the other is turned OFF, and accordingly, an output voltage of the push-pull buffer is changed in accordance with the input voltage. This will be explained later in detail.
In the above-described prior art BiCMOS push-pull type logic apparatus, however, before each of the NPN type transistors is turned ON, the voltage at the base thereof remains at a ground level. Therefore, in order to turn ON each of the NPN type transistors, first, a parasitic capacitance thereof has to be charged, which reduces the operation speed. In this case, the driving power of the CMOS control circuit is made large so as to increase the operation speed.
In order to compensate for the reduction of the operation speed, the inventor has already proposed that a voltage clamp circuit is provided at the base of each of the NPN transistors, to clamp the voltage at the base of each of the NPN transistors before turning ON the NPN transistors (see Japanese Patent Application No. 5-237620 filed on Sep. 24, 1993 and published as Kokai No. HEI7-95045 on Apr. 7, 1995). This will be explained later in detail.
In the above-proposed BiCMOS push-pull type logic apparatus, however, the output voltage swing is so small that it is impossible to operate the logic apparatus under a low power supply voltage system.